In general, a data storage system stores and retrieves data for one or more external hosts. FIG. 1 shows a high-level block diagram of a conventional data storage system 20. The data storage system 20 includes front-end circuitry 22, a cache 24, back-end circuitry 26 and a set of disk drives 28-A, 28-B (collectively, disk drives 28). The cache 24 operates as a buffer for data exchanged between external hosts 30 and the disk drives 28. The front-end circuitry 22 operates as an interface between the hosts 30 and the cache 24. Similarly, the back-end circuitry 26 operates as an interface between the cache 24 and the disk drives 28.
FIG. 1 further shows a conventional implementation 32 of the data storage system 20 that has a set of buses for carrying address information and data to and from the various data storage system components, i.e., to and from the front-end circuitry 22, the cache 24 and the back-end circuitry 26. In the implementation 32, the front-end circuitry 22 includes multiple front-end circuit boards 34. Each front-end circuit board 34 includes a pair of front-end directors 36-A, 36-B. Each front-end director 36 (e.g., the front-end director 36-A of the front-end circuit board 34-1) is interconnected between a particular host 30 (e.g., the host 30-A) and a set of M buses 38 (sometimes referred to as parallel multi-drop buses) that lead to the cache 24 (M being a positive integer), and operates as an interface between that host 30 and the cache 24. Similarly, the back-end circuitry 26 includes multiple back-end circuit boards 40. Each back-end circuit board 40 includes a pair of back-end directors 42-A, 42-B. Each back-end director 42 is interconnected between a particular disk drive 28 and the M buses 38 leading to the cache 24, and operates as an interface between that disk drive 28 and the cache 24.
Each disk drive 28 has multiple connections 44, 46 to the cache 24. For example, the disk drive 28-A has a first connection 44-A that leads to the cache 24 through the back-end director 42-A of the back-end circuit board 40-1, and a second connection 46-A that leads to the cache 24 through another back-end director of another back-end circuit board 40 (e.g., a back-end director of the back-end circuit board 40-2). The multiple connections 44, 46 provide fault tolerant features (e.g., the capability to store and retrieve data even when one of the connections 44, 46 becomes unavailable) and optimization features (e.g., the capability to load balance across the connections 44, 46).
For a host 30 to store data on the disk drives 28, the host 30 provides the data to one of the front-end directors 36. That front-end director 36 then performs a write operation by providing the data to the cache 24 through one of the M buses 38. Next, one of the back-end directors 42 reads the data from the cache 24 through one of the M buses 38 and stores the data in one or more of the disk drives 28. To expedite data transfer, the front-end director 36 can place a message for the back-end director 42 in the cache 24 when writing the data to the cache 24. The back-end director 42 can then respond as soon as it detects the message from the front-end director 36. Similar operations occur for a read transaction but in the opposite direction (i.e., data moves from the back-end director 42 to the front-end director 36 through the cache 24).